3D-IC Work

Thermal and stress modeling was part of the large amount of 3D-IC work done at RPI and Albany Nanotech, as part of the Interconnect Focus Center. That work continues at Process Evolution.

We have studied thermally induced stresses in 3D-ICs, with an emphasis on the vias that interconnect the circuits on two wafers; i.e., the 'interwafer vias' which might wee be "TSVs" (through silicon vias). We have focused our efforts on wafers glued together using BCB, and interconnected using copper interwafer vias. See the figure below. In addition to several other papers on this and related studies, see "Three-Dimensional Integration in Microelectronics: Motivation, Processing and Thermomechanical Modeling", T. S. Cale, J.-Q. Lu and R. J. Gutmann, Chem. Eng. Comm. 195, 847-888 (2008).

The goal is to determine if thermal expansion can be a reliability issue, due to the differing thermal expansion coefficients in the bonded wafers. We used Comsol Multiphysics for this phase of our thermomechanical modeling. The figure on the left above shows an idealized field of vias through muultiple materials.The image on the right above shows a view of one quarter of a via and bounding materials, as used in the simulations.

(left) A field of identical interwafer vias.
(right) A computational domain for continuum models - a quarter of a single via.
See for example: J. Zhang et al., IEEE Trans. Sem. Man. 19(4), 437-448 (2006)

Results using models that treat all of the materials in the via structure as traditional continua show that there is reason to be concerned about thermally induced stresses in BCB-bonded wafers. This is basically because BCB has a much larger coefficient of thermal expansion (CTE) than Cu. As shown in the figures below, the highest stresses induced in the copper interwafer vias are where they pass through the BCB layer.

(left) Computed von Mises stress distributions, due to a temperature change of 100 K, on cross-sections of two via structures, for two different via diameters, for the specified pitch and BCB thickness.
(right) (top)Computed von Mises stress vs. via diameter for the listed BCB thickness and via pitches
(right) (bottom) Computed von Mises stress vs. BCB thickness for the listed via diameter and via pitches
See for example: J. Zhang et al., IEEE Trans. Sem. Man. 19(4), 437-448 (2006)

Note that for a fixed BCB thickness and pitch, the smaller via diameter has the larger von Mises stresses in the copper as it passes through the BCB. Depending upon the values of such design parameters, there may be problems with stability, as the stresses can be beyond reasonable estimates of yield strength.

To improve our model for 3D-IC via structures, we introduced grain structures, as it is easy to show that polycrystalline models of copper can result in very different induced stresses than models that treat copper as homogeneous.

PLENTE is used to generate and represent the grains in polycrystalline models of 3D-IC vias. As the region of most interest is the via as it passes through the BCB layer, we focus our attention there. In order to reduce the computational burden of representing the entire via as grains, we studied how much of the via needed to be represented as grains. That is, we computed the stresses induced in the region of the BCB layer, using granular representations of different lengths of the via. We found that We needed to represent about the via a grains for about 1 grain size outside of the BCB layer.

(left) Schematic of a cross section of a via structure, in which the copper is represented partly as a granular material (near the BCB layer), and partly as a homogeneous material (away from the BCB layer).
(right) A different view of the HGC representation of the simulation volume, which is a full via (rather than 1/4 of a via).
See for example: D.N. Bentz et al., J. Comp. Elect. 5(4), 327-331 (2006)
D.N. Bentz et al. Microelect. Eng. (2007), doi:10.1016/j.mee.2007.06.006.

After developing this hybrid of traditional continuum and grain-continuum approaches, which we call a 'hybrid grain-continuum' or HGC repressentation of the structure, we compared computed maximum induced von Mises stresses against those from tradtional continuum (TC) models of via structures.

We compare the results of HGC and TC models by using PLENTE and COMSOL Multiphysics as a virtual testbed to generate DoE (Design of Experiments) models for the same region of design parameter space. In this study, two values (levels) were chosen for (each) via diameter, via pitch and BCB thickness, and a temperature change of 100 K was considered.

(left) DoE interaction summary for traditional continuum (TC) models.
(right) DoE interaction summary for Hybrid grain-continuum (HGC) models.

For the same design parameters, the trends are the same (qualitatively the same results for TC and HGC models), but the maximum von Mises stresses induced by the temperature change are higher when using HGC models than when using TC models.

Given a distribution of stress and strains throughout the domain of an HGC representation, the motion of the grain boundaries can be computed. Some results are summarized by the following figures. An image of strain energy density on a cross section of a 3D-IC via is shown on the left. On the top right are images that show how the HGC approach was used to predict evolution. The graph on the bottom right shows that strain energy driven evolution is slower than curvature driven evolution.

(left) Distribution of strain energy density along a cross section of an HGC model. Jumps across grain boundaries are difficult to see, but are large enough to drive significant grain boundary motion.
(right) (top) Initial motion of the grain boundaries, induced by jumps in strain energy - for a somewhat different set of grains than in the image on the left. Note the lines that delineate the BCB layer.
(right) (bottom) A graph that compares the evolution speeds due to strain energy to the evolution speeds due to curvature. (Note that the affected grains may well be in different parts of the metal.)

PE Home        About PE        Contact PE
EVOLVE AMR   EVOLVE MM   EVOLVE 3D   EVOLVE   3D-ICs   PLENTE